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TM
HSP45256/883
Binary Correlator
The Intersil HSP45256/883 is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256's can be cascaded for increased correlation length. Unused taps can be masked out for reduced correlation length. The correlation array consists of eight 32-tap stages. These may be cascaded internally to compare 1, 2, 4 or 8-bit input data with a 1-bit reference. Depending on the number of bits in the input data, the length of the correlation can be up to 256, 128, 64, or 32 taps. The HSP45256 can also be configured as two separate correlators with window sizes from 4 by 32 to 1 by 128 each. The Mask Register can be used to prevent any subset of the 256 bits from contributing to the correlation score. The9- output of the correlation array (correlation score) feeds the weight and sum logic, which gives added flexibility to the data format. In addition, an offset register is provided so that a preprogrammed value can be added to the correlation score. This result is then passed through a user programmable delay stage to the cascade summer. The delay stage simplifies the cascading of multiple correlators by compensating for the latency of previous correlators. The Binary Correlator is configured by writing a set of control registers via a standard microprocessor interface. To simplify operation, both the Control and Reference Registers are double buffered. This allows the user to load new mask and reference data while the current correlation is in progress.
December 1999
Features
CT CT RODU RODU ET E P UTE P ERSIL SO L OB BSTIT 88-INT LE S U -8 OSSIB lications 1 rsil.com P FOR A tral App inte en t a pp@ call C email: cen or Description
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Reconfigurable 256 Stage Binary Correlator * 1-Bit Reference x 1, 2, 4, or 8-Bit Data * Separate Control and Reference Interfaces * Configurable for 1-D and 2-D Operation * Double Buffered Mask and Reference * Programmable Output Delay * Cascadable * Standard Microprocessor Interface
Applications
* Radar/Sonar * Spread Spectrum Communications * Pattern/Character Recognition * Error Correction Coding
Ordering Information
PART NUMBER HSP45256GM-20/883 HSP45256GM-25/883 TEMP. RANGE ( oC) -55 to 125 -55 to 125 PACKAGE 85 Ld CPGA 85 Ld CPGA PKG. NO. G85.A G85.A
Block Diagram
DOUT0-7 DIN0-7 DREF0-7 WEIGHT AND SUM 256 TAP CORRELATION ARRAY
MUX
AUXOUT0-8
DCONT0-7 CONTROL A0-2 DELAY
CASCADE SUMMER CASOUT0-12
CASIN0-12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN2997.4
1
HSP45256/883 Pinouts
1 A 2 3 4
85 PIN PGA TOP VIEW
5 6 7 CAS OUT 0 CAS OUT 1 OEC 8 CAS OUT 3 CAS OUT 4 9 CAS OUT 5 CAS OUT 6 10 GND CAS OUT 7 CAS OUT 9 GND 11 CAS OUT 8 CAS OUT 10 CAS OUT 11 CAS OUT 12 CASIN CASIN CASIN CASIN CASIN CASIN 2 4 5 7 10 11 GND CASIN CASIN CASIN CASIN 1 3 6 9 CASIN INDEX PIN 0 VCC CAS OUT 2
B
C
CLK
CASIN CASIN 12 8
D
DIN7
E F
DIN4 DREF 6 DIN0
DIN5 DIN3 DREF 7
DIN6 DIN2
DOUT0 DOUT1 DOUT2 DOUT DOUT 4 7 VCC DOUT 6 AUX OUT 1 A1 DCONT DCONT 5 4 DCONT DCONT OEA 6 2 AUX OUT 6 AUX OUT 8 GND AUX OUT 4 AUX OUT 7 DOUT 3 DOUT 5 AUX OUT 0 AUX OUT 2 AUX OUT 3 AUX OUT 5
G
DIN1
H
DREF DREF 5 4 DREF DREF 3 1 DREF 2 DREF 0 VCC GND R LOAD TXFR C LOAD A2
J
K
A0
L
DCONT DCONT DCONT DCONT 7 1 3 0
85 PIN PGA BOTTOM VIEW
L DREF0 K DREF2 V CC RLOAD CLOAD A0 DCONT 6 DCONT 2 OEA AUXOUT 6 AUXOUT 4 AUXOUT 3 GND TXFR A2 DCONT 7 DCONT 1 DCONT 3 DCONT0 AUXOUT 8 AUXOUT 7 AUXOUT 5
J DREF3 DREF1 A1 DCONT 5 DCONT 4 GND AUXOUT 2
H DREF5 G DIN0 F DREF6 E DIN4 D DIN7 VCC GND CASOUT 12 DIN5 DIN6 DOUT0 DOUT1 DOUT2 DIN3 DIN2 DOUT4 DOUT7 DOUT3 DREF7 DIN1 VCC DOUT6 DOUT5 DREF4 AUXOUT 1 AUXOUT 0
C CLK CASIN0 INDEX PIN CASIN 8 CASIN 12 OEC CASOUT 9 CASOUT 11
B GND CASIN1 CASIN3 CASIN6 CASIN 9 CASOUT 2 CASOUT 1 CASOUT CASOUT 4 6 CASOUT 7 CASOUT 10
A CASIN 2 1 CASIN 4 2 CASIN 5 3 CASIN 7 4 CASIN 10 5 CASIN 11 6 CASOUT CASOUT 0 3 7 8 CASOUT 5 9 GND 10 CASOUT 8 11
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HSP45256/883 Pin Description
SYMBOL VCC GND DIN0-7 PIN NUMBER D2, G9, K2 A10, B1, D10, J10, L2 D1, E1-E3, F2, F3, G1, G3 E9-E11, F9-F11, G10, G11 C1 A1-A6, B2-B5, C2, C5, C6 A7-A9, A11, B6-B11, C10, C11, D11 I TYPE The +5V power supply pin. Ground. The DIN0-7 bus consists of eight single data input pins. The assignment of the active pins is determined by the configuration. Data is loaded synchronous to the rising edge of CLK. DIN0 is the LSB. The DOUT0-7 bus is the data output of the correlation array. The format of the output is dependent on the window configuration and bit weighting. DOUT0 is the LSB. System Clock. Positive edge triggered. CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of one correlator to CASIN0-12 of another. The CASIN bus is added internally to the correlation score to form CASOUT. CASIN0 is the LSB. CASOUT0-12 is the output correlation score. This value is the delayed sum of all the 256 taps of one chip and CASIN0-12. When the part is configured to act as two independent correlators, CASOUT0-8 represents the correlation score for the first correlator while the second correlation score is available on the AUXOUT0-8 bus. In this configuration, the cascading feature is no longer an option. CASOUT0 is the LSB. OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stated. Processing is not interrupted by this pin (active low). TXFR is a synchronous clock enable signal that allows the loading of the reference and mask inputs from the preload register to the correlation array. Data is transferred on the rising edge of CLK while TXFR is low (active low). DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load the reference data. RLOAD going active initiates the loading of the reference registers. This input bus is used to load the reference registers of the correlation array. The manner in which the reference data is loaded is determined by the window configuration. If the window configuration is 1 x 256, the reference bits are loaded one at a time over DREF7. When the HSP45256 is configured as an 8 x 32 array, the data is loaded into all stages in parallel. In this case, DREF7 is the reference data for the first stage and DREF0 is the reference data for the eighth stage. The contents of the reference data registers are not affected by changing the window configuration. DREF0 is the LSB. RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the preload registers on the rising edge of RLOAD. This data is transferred into the correlation array by TXFR (active low). DCONT0-7 is the control data input, which is used to load the mask bit for each tap as well as the configuration registers. The mask data is sequentially loaded into the eight stages in the same manner as the reference data. DCONT0 is the LSB. CLOAD enables the loading of the data on DCONT0-7. The destination of this data is controlled by A0-2 (active low). A0-2 is a 3-bit address that determines what function will be performed when CLOAD is active. This address bus is set up with respect to the rising edge of the load signal, CLOAD. A0 is the LSB. AUXOUT0-8 is a 9-bit bus that provides either the data reference output or the 9-bit correlation score of the second correlator, depending on the configuration. When the user programs the chip to be two separate correlators, the score of the second correlator is output on this bus. When the user has programmed the chip to be one correlator, AUXOUT0-7 represents the reference data out, with the state of AUXOUT0-8 undefined. AUXOUT0 is the LSB. The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the output is disabled. Processing is not interrupted by this pin (active low). Used for orienting pin in socket or printed circuit board. Must be left as a no connect in circuit. DESCRIPTION
DOUT0-7 CLK CASIN0-12
O I I
CASOUT0-12
O
OEC TXFR
C7 L3
I I
DREF0-7
F1, G2, H1, H2, J1, J2, K1, L1
I
RLOAD
K3
I
DCONT0-7
J6, J7, K6, K7, L5-L8 K4 J5, K5, L4
I
CLOAD# A0-2
I I
AUXOUT0-8
H10, H11, J11, K9-K11, L9-L11
O
OEA Index Pin
K8 C3
I
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HSP45256/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
JC Thermal Resistance (Typical, Note 1). . . JA PGA Package . . . . . . . . . . . . . . . . . . . 36oC/W 10oC/W Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13,000 Gates
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Logical One Input Voltage Clock Logical Zero Input Voltage Clock Output HIGH Voltage
SYMBOL VIH
CONDITIONS VCC = 5.5V
TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
MIN 2.2
MAX -
UNITS V
VIL
VCC = 4.5V
1, 2, 3
-
0.8
V
VIHC
VCC = 5.5V
1, 2, 3
3.0
-
V
VILC
VCC = 4.5V
1, 2, 3
-
0.8
V
VOH
IOH = -400A VCC = 4.5V (Note 2) IOL = +2.0mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 5.5V VIN = VCC or GND VCC = 5.5V VIN = VCC or GND VCC = 5.5V, Outputs Open f = 20 MHz, VIN = VCC or GND, VCC = 5.5V (Note 3) (Note 4)
1, 2, 3
2.6
-
V
Output LOW Voltage Input Leakage Current
VOL
1, 2, 3
-
0.4
V
II
1, 2, 3
-10
+10
A A A
Output Leakage Current
IO
1, 2, 3
-10
+10
Standby Power Supply Current
ICCSB
1, 2, 3
-
500
Operating Power Supply Current
ICCOP
1, 2, 3
-55 TA 125
-
140
mA
Functional Test NOTES:
FT
7, 8
-55 TA 125
-
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 7mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, VIL = 0.4V, VOH 1.5V, and VOL 1.5V.
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HSP45256/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (Note 5) GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -25 (25.6MHz) TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 39 15 15 39 15 15 39 15 15 13 1 14 1 13 1 13 1 13 1 MAX 20 -20 (20MHz) MIN 50 20 20 50 20 20 50 20 20 15 1 15 1 15 1 15 1 15 1 MAX 25 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER CLK Period CLK High CLK Low CLOAD Cycle Time CLOAD High CLOAD Low RLOAD Cycle Time RLOAD High RLOAD Low Set-up Time; DIN to CLK High Hold Time; DIN to CLK High Set-up Time; DREF to RLOAD High Hold Time; DREF to RLOAD High DCONT Set up Time DCONT Hold Time Address Set up Time Address Hold Time TXFR Set up Time TXFR Hold Time CLK to Output Delay DOUT, AUXOUT, CASOUT Output Enable Time TXFR High to CLK Low CLK Low to RLOAD, CLOAD High NOTES:
SYMBOL t CP t CH t CL t CLC t CLH t CLL t RLC t RLH t RLL t DS t DH t RS t RH t DCS t DCH t AS t AH t TS t TH t DO
(NOTE 5) NOTES
t OE t THCL t CLLH
Note 6 Note 7 Note 7
9, 10, 11 9, 10, 11 9, 10, 11
-55 TA 125 -55 TA 125 -55 TA 125
3 1
20 -
4 1
20 -
ns ns ns
5. AC testing is performed as follows: VCC = 4.5V and 5.5V. Input levels (CLK input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; Timing reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with CL = 40pF. Output transition is measured at VOH 1.5V and VOL 1.5V. 6. Transition is measured at 200mV from steady state voltage, Output loading per test load circuit, CL = 40pF. 7. Applicable only when TXFR and RLOAD or CLOAD are active on the same cycle of CLK.
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HSP45256/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS -25 PARAMETER Input Capacitance Output Capacitance Output Disable Time Output Rise Time Output Fall Time NOTES: 8. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 9. Loading is as specified in the test load circuit with CL = 40pF. SYMBOL CIN COUT CONDITIONS VCC = Open, f = 1MHz All measurements are referenced to device GND. NOTES 8 8 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN MAX 10 10 MIN -20 MAX 10 10 UNITS pF pF
tOD
8, 9
-
20
-
20
ns
tR tF
From 0.8V to 2.0V From 2.0V to 0.8V
8, 9 8, 9
-
8 8
-
8 8
ns ns
TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
Test Load Circuit
S1 DUT (NOTE) C L
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
SWITCH S1 OPEN FOR ICCSB AND I CCOP TEST
NOTE: Includes stray and jig capacitance.
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HSP45256/883 Timing Waveforms
tCP tCH CLK tCLH tDS DIN0-7 tDH CLOAD tAS tTS tTH A0-7 tAH tCL t CLC tCLL
tTS
TXFR tDO DOUT0-7 CASOUT0-12, AUXOUT0-8
tCS DCONT0-7
tCH
FIGURE 1. INPUT, OUTPUT TIMING
FIGURE 2.
tRLC tRLL RLOAD tOD tAS A0-2 tr, tf DOUT0-7, CASOUT0-12 AUXOUT0-8
2.0V 0.8V
tRLH
OEA, OEC
tOE 1.7V 1.3V
tAH
AUXOUT0-8 CASOUT0-12
tRS DREF0-7
tRH
FIGURE 3.
FIGURE 4.
tCLLH tTHCL CLK
TXFR
RLOAD, CLOAD
FIGURE 5. TRANSFER, LOAD TIMING WHEN BOTH OCCUR ON A SINGLE CYCLE
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HSP45256/883 Burn-In Circuits
85 PIN PGA TOP VIEW
1 A 2 3 4 5 6 7 CAS OUT 0 CAS OUT 1 OEC 8 CAS OUT 3 CAS OUT 4 9 CAS OUT 5 CAS OUT 6 10 GND CAS OUT 7 CAS OUT 9 GND 11 CAS OUT 8 CAS OUT 10 CAS OUT 11 CAS OUT 12
CASIN CASIN CASIN CASIN CASIN CASIN 2 4 5 7 10 11 GND CASIN CASIN CASIN CASIN 1 3 6 9 CASIN INDEX PIN 0 VCC CAS OUT 2
B
C
CLK
CASIN CASIN 8 12
D
DIN7
E
DIN4 DREF 4 DIN0
DIN5
DIN6
DOUT0 DOUT1 DOUT2
F
DIN3 DREF 7 DREF 4 DREF 1 VCC
DIN2
DOUT 4 VCC
DOUT 7 DOUT 6 AUX OUT 1
DOUT 3 DOUT 5 AUX OUT 0 AUX OUT 2 AUX OUT 3 AUX OUT 5
G
DIN1
H
DREF 5 DREF 3 DREF 2 DREF 0
J
A1 R LOAD TXFR C LOAD A2
DCONT DCONT 5 4 DCONT DCONT OEA 6 2 AUX OUT 6 AUX OUT 8
GND AUX OUT 4 AUX OUT 7
K
A0
L
GND
DCONT DCONT DCONT DCONT 7 1 3 0
PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2
PIN NAME CASIN2 CASIN4 CASIN5 CASIN7 CASIN10 CASIN11 CASOUT0 CASOUT3 CASOUT5 GND CASOUT8 GND CASIN1
BURN-IN SIGNAL F3 F5 F6 F1 F4 F5
PGA PIN B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1
PIN NAME CASOUT10 CLK CASIN0 CASIN8 CASIN12 OEC CASOUT9 CASOUT11 DIN7
BURN-IN SIGNAL
PGA PIN F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11
PIN NAME DOUT4 DOUT7 DOUT3 DIN0 DREF7 DIN1
BURN-IN SIGNAL
PGA PIN K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3
PIN NAME
BURN-IN SIGNAL
VCC/2
F0 F1 F2 F6 F11
VCC/2 VCC/2 VCC/2
F1 F8 F2
VCC
RLOAD CLOAD A0 DCONT6 DCONT2 OEA AUXOUT6 AUXOUT4 AUXOUT3 DREF0 GND TXFR
VCC
F3 F3 F9 F7 F6 F11
VCC/2 VCC/2 VCC/2
GND
VCC/2 VCC/2
F8
VCC
DOUT6 DOUT5 DREF5 DREF4 AUXOUT1 AUXOUT0
VCC VCC/2 VCC/2
F6 F8
VCC/2 VCC/2 VCC/2
F4 GND F2
VCC
GND CASOUT12 DIN4
VCC
GND
VCC/2
GND F2
VCC/2
F5
VCC/2 VCC/2
9-8
HSP45256/883
(Continued)
PGA PIN B3 B4 B5 B6 B7 B8 B9 B10 PIN NAME CASIN3 CASIN6 CASIN9 CASOUT2 CASOUT1 CASOUT4 CASOUT6 CASOUT7 BURN-IN SIGNAL F4 F7 F3 PGA PIN E2 E3 E9 E10 E11 F1 F2 F3 PIN NAME DIN5 DIN6 DOUT0 DOUT1 DOUT2 DREF6 DIN3 DIN2 BURN-IN SIGNAL F6 F7 PGA PIN J1 J2 J5 J6 J7 J10 J11 K1 PIN NAME DREF3 DREF1 A1 DCONT5 DCONT4 GND AUXOUT2 DREF2 BURN-IN SIGNAL F7 F5 F10 F6 F8 GND L4 L5 L6 L7 L8 L9 L10 L11 PGA PIN A2 DCONT7 DCONT1 DCONT3 DCONT0 AUXOUT8 AUXOUT7 AUXOUT5 PIN NAME BURN-IN SIGNAL F11 F8 F5 F7 F4
VCC/2 VCC/2 VCC/2
F7 F4 F3
VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
VCC/2 VCC/2 VCC/2
VCC/2
F6
NOTES: 10. V CC/2 (2.7V 10%) used for outputs only. 11. 47k (20%) resistor connected to all pins except VCC and GND. 12. V CC = 5.5 0.5V. 13. 0.1F (min) capacitor between V CC and GND per position. 14. FO = 100kHz 10%, F1 = F0/2, F2 = F1/2 . . . F11 = F10/2, 40 - 60% Duty Cycle. 15. Input Voltage Limits: VIL = 0.8V max, VIH = 4.5 10%.
Metal Topology
DIE DIMENSIONS: 254 mils x 214 mils x 19 1 mil METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 0.96 x 105 A/cm 2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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